Programmable logic devices are increasingly being incorporated as part of a system design and employed for a broad range of applications. Consequently, special functional blocks (SFBs) are often embedded into the programmable logic device (PLD) to meet the desired requirements (e.g., high speed interface requirements). For example, a SFB may include a phase-locked loop (PLL) or a delay-locked loop (DLL) along with high-speed input/output (I/O) circuits and memory interface controllers to help support the application requirements (e.g., system-on-a-chip requirements).
SFBs typically have some programmable options controlled by configuration memory cells within the programmable logic device. Often most of these programmable options may be determined during the design phase and set via the configuration bitstream, with no further changes required after the initial configuration. However, some of the programmable options may require dynamic adjustments or fine tuning (e.g., field adjustments while on the circuit board) after the initial configuration has been completed to find the best setting for a specific device and environment. For example, the duty cycle option of a PLL within a PLD may be fixed in design and on board, but the voltage-controlled oscillator (VCO) tap options guarding the frequency may have to be adjusted through trial and error for each specific device containing the PLD due to slight performance differences between devices.
One technique for providing dynamic adjustments is to perform partial reconfiguration. For example, the default settings for the SFB's programmable options are initially downloaded into the PLD (e.g., a field programmable gate array (FPGA), a complex programmable logic device (CPLD), or a programmable interconnect device). If one or more of the default settings are not correct, the default settings may be changed via a partial reconfiguration bitstream while the PLD retains its remaining configuration settings and may remain in a user-defined operating mode. One drawback of this technique is the complexity associated with partial reconfiguration control and the inefficiency of downloading a partial reconfiguration bitstream for the relatively few bits required for an SFB adjustment.
Another technique is to embed a system bus into a PLD and hardwire every SFB onto the system bus so that the configuration memory cells of each SFB are utilized as system bus registers. Each SFB can then be independently reconfigured by data transfers via the embedded system bus while avoiding bitstream downloading associated with partial reconfiguration techniques. Further details regarding an exemplary system bus may be found in U.S. Pat. No. 6,483,342, which is incorporated herein by reference in its entirety.
One drawback of the system bus technique is the layout difficulty often encountered to hardwire the system bus to all of the SFBs within the PLD (e.g., due to the extensive dedicated routing and buffering). Furthermore, if a user only requires access to the configuration memory cells associated with one of the SFBs, the entire system bus must be enabled. Additionally, the fixed bus address associated with each SFB's register may also limit software placement of an SFB for a user's desired application. As a result, there is a need for improved techniques for accessing memory within a PLD.